• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
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  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    Semiconductor devices, in particular ball grid arrays or chip scale packages, form a generally flat surface comprising an integrated circuit chip having at least one input / output terminal and at least one ridge having a size and shape suitable to mimic a solder ball. And a body of encapsulated material molded around the chip, wherein the ridge has a conductive solderable surface connected to the terminal.
    公开号:KR20000071375A
    申请号:KR1020000008936
    申请日:2000-02-24
    公开日:2000-11-25
    发明作者:카터버포드에이치.；데이비스데니스디.；키이데이비드알.
    申请人:윌리엄 비. 켐플러；텍사스 인스트루먼츠 인코포레이티드；
    IPC主号:
    专利说明:

    INTEGRATED CIRCUIT DEVICE WITH ELEVATIONS SIMULATING SOLDER BALLS AND METHOD OF FABRICATION}
    FIELD OF THE INVENTION The present invention relates generally to the field of semiconductor devices and processes, and more particularly to methods of manufacturing raised low cost ball grid arrays and ridges that mimic chip scale packages and solder balls.
    The trend in semiconductor technology (Moore's law), which multiplies the product's functional complexity every 18 months, is still valid today and has some absolute consequences after dominating the industry for the past 30 years. First, the cost per functional unit falls for each generation of complexity, thus only slightly increasing the cost of a product with doubled functionality. Second, higher product complexity is achieved primarily by reducing the specific size of the chip components while keeping the package dimensions constant or preferably shrinking the package. Third, increased functional complexity goes hand in hand with a corresponding increase in product reliability. Fourth, the most financial benefits are guaranteed to those who are ahead of the competition, especially in reaching the goals of complexity while delivering the most applicable products.
    Plastic ball grid arrays (BGAs) and chip scale packages (CSPs) have been used in the past few years, but many drawbacks have limited their application of the trend to Moore's Law. The high content of plastic materials and the fixed number of manufacturing process steps made it difficult to reduce the cost of BGAs and CSPs. The reliability of plastic BGAs and CSPs is compromised by their sensitivity to thermal-mechanical stresses and moisture absorption. It is difficult to adapt the package design to the ordered requirements, so the package design does not have sufficient applicability to meet the general application trend for smaller package outlines and thinner profiles.
    Known techniques pay attention to improving the design of BGA and CSP packages and processes on devices with high lead counts (or solder ball counts), overlooking the specific needs of BGAs and CSPs for smaller lead counts (solder balls). do. Thus, a wide range of applications cannot be obtained, especially requiring a small number of solder balls.
    In this situation in the art, plastic packages with small pin counts use stamped or etched lead frames, which lead to the majority of material costs in such packages. Plastic BGAs and CSPs use patterned polyimide films as substrates for mounting semiconductor chips, which account for most of the material costs in these packages. In addition, the techniques used in the art for attaching solder balls (or protrusions) to packages are unsatisfactory because of problems related to ball bonding, ball loss or ball overlap. The manufacturing process adopted and the required inspection hinder cost reduction.
    According to the invention for an integrated circuit (IC) device, a forming process for encapsulating the device is used to form a ridge of the appropriate size and shape that mimics a solder ball, which is electrically connected to the input / output terminals of the IC chip. It is configured to have a conductive solderable surface connected.
    DETAILED DESCRIPTION OF THE INVENTION The present invention relates to high density ICs, in particular ICs having a small or moderate number of input / output or bonding pads, devices using conductive or metal substrates to which devices are typically connected by wire bonding, and small package outlines and low profile It relates to a device requiring a. Such ICs are found in many semiconductor devices such as processors, digital and analog devices, mixed signal and standard linear logic products, telephones, RF and telecommunications devices, intelligent power devices, and large and small area chip categories. The present invention allows ensuring basic characteristics and reliability in applications such as wireless communications, pagers, hard disk drives, laptop computers and medical devices.
    The present invention provides for the modification and simplification of some of the materials in the basic process steps typically practiced in semiconductor assembly and packaging techniques, thereby reducing significant manufacturing costs. The chip is mounted on a substrate provided as a thin foil in the thickness range of about 10 μm to 75 μm. In this thickness range, the foil responding to pressure during the conventional transfer molding process moves against the steel wall of the mold cavity and is smoothly aligned with the surface contour of the wall. Thus, ridges of conductive material that have a solderable surface and mimic the solder " ball " can be created and used at the time of solder attachment. The amount of elongation that can be stretched so that the foil material becomes the curved configuration in the original flat configuration is determined by the present invention. Ball-mimetic bumps can be produced at a height between about 150 μm and 230 μm using a peristaltic foil of about 30 μm to 40 μm thick.
    Aspects of the present invention are applicable to a variety of different ball grid arrays and chip scale packages, in particular ball grid arrays and chip scale packages having about 4 to 80 "balls". The most used range is about 8 to 48 "balls".
    Another aspect of the invention is to provide a technique for producing low "lead" inductances in a product for many applications.
    Another aspect of the invention is to eliminate the difficulty of positioning the preformed solder balls on the device package by creating ball-mimicking bumps simultaneously with the package.
    Another aspect of the present invention is to improve package reliability by improving adhesion between the metal composite and the casting composite used for electrical connection to the outside.
    Another aspect of the present invention is to contribute to device space maintenance by introducing manufacturing steps that contribute to the trend towards packages with low overall profiles and small outlines.
    Another aspect of the present invention is to improve product quality by process unification, to control thermal-mechanical stress, to minimize moisture absorption, and to improve reliability guarantee by general process control at no additional cost.
    Another aspect of the present invention is to introduce an assembly concept for a general thin profile package that is highly applicable to many types of semiconductor products and can be applied to the next generation of products.
    These aspects are made by the present invention in connection with a method suitable for mass production. Various modifications are successfully adopted to meet different choices of shape and material of the product.
    In one embodiment of the present invention, the size of the ball mimic ridges and the stretch of the foil material required to form these ridges are used to make certain low profile devices.
    In another embodiment of the present invention, a configuration in a predetermined number of raised and simulated rows of "balls" is used to fabricate devices of a given ball grid array and small chip scale package outline.
    Aspects of the present invention as well as technical improvements by the present invention are apparent from the following description of the preferred embodiments of the present invention when considered in connection with the novelty shown in the appended claims and the accompanying drawings.
    1A, 1B and 1C are schematic views of a ball grid array element having 40 " balls " according to an embodiment of the present invention, FIG. 1A is a plan view of a ball grid array element, and FIG. 1B is a ball grid according to the present invention. 1C is a schematic bottom view of a ball grid array package according to the present invention.
    2 is a schematic cross-sectional view of a portion of a ball grid array in accordance with the present invention.
    3A-3C are schematic cross-sectional views of a mold cavity showing a manufacturing process of the device according to the present invention.
    Fig. 3D is a schematic cross sectional view of a device produced by the process of the present invention.
    <Explanation of symbols for the main parts of the drawings>
    101: plastic encapsulation material
    112: uplift
    300: mold
    301: upper mold half
    302: lower half of the mold
    303: Mold Joint
    305: dimple
    306: Chip
    307: conductive sheet type substrate
    308: wire
    The present invention relates to an integrated circuit (IC) having a small outline and low profile ball grid array (BGA) and chip scale package (CSP). As defined herein, the term "outline" refers to the overall width and length of the IC package of the present invention. The outline of a package is also referred to as the footprint of the package because the outline forms the surface area on the wiring board or assembly board that the package occupies. The term "chip scale package" is used in two senses. In the first sense, the package has an outline that adds to the chip area by less than 20%, and a chip scale package that is only the size of the chip itself is often referred to as a "chip size package". In the second sense, "chip scale package" simply means a small size BGA.
    The term "profile" means the thickness or height of an IC package. This definition does not include the height of the solder balls before they are reflowed upon board attachment.
    As used herein, the term solder "ball" does not mean that the solder contact must be spherical. The balls may have a variety of shapes, such as hemispherical, semi-domed, truncated cone or general protrusion. The exact shape is a function of deposition techniques (such as deposition, plating or prefabrication units), reflowing techniques (such as infrared or radiant heat) and material composition. Several methods are available to achieve geometrical consistency by controlling the amount of material and the uniformity of the reflowing temperature. Solder “balls” can include lead / tin mixtures or conductive adhesive composites.
    As an example of a preferred embodiment of the present invention, FIGS. 1A-1C are different views of a square BGA for 40 connections. 1A is a plan view of a package showing a plastic encapsulation material 101 (an epoxy-based thermoset material commonly used in transfer molding processes) forming a generally flat surface 103. Although the side length 102 in the example of FIG. 1A is 8.0 mm, the present invention can be readily applied to BGA and CSP devices having a square or rectangular outline and a side length in the range of about 4.0 to 12.0 mm.
    1B is a side view of the same BGA with a portion shown in cross section. The package has a generally flat top surface 103 and a generally flat bottom surface 116. In this example, the thickness 114 of the package is 1.0 mm. As shown by the cross section (hatched portion 115), the molded plastic 111 extends into all the elevations 112 protruding from the generally flat bottom surface 116. It is an important aspect of the present invention that such ridges 112 are formed in the same plastic molding process employed to encapsulate the device. This ridge 112 may be formed as part of a sphere and mimics a portion of the solder “ball”. Thus, the bumps are also referred to as "knolls." Other shapes of the ridges 112 include truncated cones or truncated pyramids or any other three dimensional shape that can be readily manufactured. 1B shows an array of some such ridges 113. The metallized portion 117 of the ridge and its thickness 117a are shown in more detail in FIG.
    In the bottom view of the BGA package, FIG. 1C shows that two rows of these ridges 112 arranged as solder balls are in a conventional BGA. In the example of Fig. 1C, there are 40 ridges in total. Although the present invention can be applied to any number of bumps, a good number is between four and eighty. The pitch 122 between the ridges in the example of FIG. 1C is 1.0 mm, and the separator 123 between the ridges may be 20 μm to 200 μm in width. The present invention is applicable to any configuration of bumps, including the creation of "dummy" bumps that do not serve as electrical connections.
    The electrical function and a more detailed description of the ridge is schematically illustrated in FIG. 2 showing some cross sections of the BGA example of FIG. 1B. The pressure applied to the composite 201 during the molding process forms a ridge 202. The height 203 of the ridge ranges from about 0.1 mm to 0.25 mm and the diameter 204 at the base of the hemisphere is between about 0.5 mm to 0.75 mm.
    It is very important for the present invention that the outside of the ridge has a conductive and solderable surface 205. The outer side of the dimple includes a metal foil having a thickness 206 that ranges between about 10 μm and 75 μm. The preferred thickness range of the metal foil is about 30 μm to 40 μm. The foil can be made of a material selected from the group comprising copper, copper alloys, iron-nickel alloys, aluminum, steel and invar. Suitable copper and copper alloy foils are produced, for example, by Olin Corporation, Waterbury, Connecticut.
    The solderable surface of the foil facing the outside of the ridge is selected from the group comprising copper, nickel, palladium, silver, gold and platinum. Another option is a deposited layer of tin-lead, tin-silver, tin-indium and other solder alloys covering the outside of the ridges. Preferred embodiments are clean copper and highly activated solder paste for attachment to the motherboard. The choice of material depends on the solder reflowing technique adopted (eg, time-temperature process, availability of solder paste or flux).
    2 shows the ridge 202 electrically connected to a terminal of an integrated circuit by a wire bond 207 (see also FIGS. 3A-3D). In accordance with a conventional wire bonding technique, the bonding wire is attached to the metal of the bump and the ball of the bonding wire with respect to the terminal (contact pad) of the IC chip.
    For electrical separation, the metal foils covering the ridges must be mechanically separated from each other. This is represented by the grooves 208 created by mechanical cutting, for example, using saw blades (width between about 130 μm and 170 μm).
    The hemispherical ridges significantly increase the area of adhesion between the casting composite and the metal foil. Thus, the adhesive strength is significantly higher and a package is produced that is significantly less susceptible to peeling by stress or moisture, as produced by the present invention.
    3A-3D show a method for manufacturing an IC device according to the present invention. In FIG. 3A, a schematic cross-sectional view of the mold 300 shows the upper half 301, lower half 302, and cavity 303 of the mold. The mold lower half 302 features a generally flat surface profile 304 that includes a plurality of dimples 305. These dimples are sized and shaped for the purpose of creating shaped bumps that mimic the solder balls in the device to be encapsulated. The edge 305a of the dimple 305 is polished so as not to be a sharp edge. The dimples can have a shape selected from the group comprising hemispherical, truncated cone, truncated pyramid and associated shapes that can be produced in cast steel at low cost.
    3A further shows the cavity 303 holding the preassembled IC chip 306. In other embodiments of the present invention, a plurality of IC chips and / or other electrical components may be preassembled. The chip 306 may be attached onto the first surface 307a of the conductive sheet-like substrate 307 and according to the present invention, the substrate is preferably a metal foil about 10 μm to 75 μm thick. The second surface 307a of the substrate 307 is prepared to be solderable. Chip attachment is by means of an adhesive epoxy or polyamide film. The input / output terminal of the chip 306 is preferably connected to the substrate 307 by a wire 308. Typically, the wire 308 is connected to the chip terminal by ball bonding and to the substrate by stitch bonding, but wedge bonding at both ends of the wire is also possible.
    The chip pre-assembled on the substrate is positioned on the mold lower half 302 such that the location 309 where the wire is welded onto the substrate 307 is aligned with respect to the position of each dimple 305 of the mold lower half. This alignment is indicated generally at 310 as shown in FIG. 3B.
    As shown in FIG. 3C, encapsulation material 311 is pressed into cavity 303 until the cavity is filled with material. Preferably, transfer molding processes and controls established in connection with epoxy-based casting composites are used (the transfer temperature is typically between about 170 ° C. and 180 ° C. and the transfer time is between about 6 seconds and 18 seconds). The ram pressure, which produces pressure in the mold cavity between about 5516 kPa (1600 psi) and 11032 kPa (1600 psi) (depending on cavity size), is typically between about 3447.5 kPa (500 psi) and 4826.5 kPa (700 psi). At the forming process and at this pressure, it is important for the present invention that the foil 307 is moved relative to the surface contour of the mold lower half 302, in particular onto the mold dimple 305. Thereafter, the casting temperature drops within about 90 seconds to 130 seconds, and the casting composite is at least partially cured and polymerized so that the mold can be opened. Thus, shaped bumps 312 are created on the body of cured encapsulation material surrounded by foil 307 on the outer raised surface. As shown in FIG. 3C, each ridge has a wire bond connecting dimples to each terminal of the chip 306. As shown in FIG.
    As mentioned above, the formation of ridges significantly increases the surface area between the casting composite and the ridge foil and thus enhances the adhesion between the casting composite and the metal foil, thereby reducing stress and moisture sensitivity of the finished device and thus improving reliability. .
    3d shows the completed device 320. In this device, the ridges 312 are electrically separated from each other by the opening 313. Such openings can be cut by high speed saws, focused lasers, high pressure liquid jets or other low cost techniques. The formation of the ridges moves the conductive foil out of the high shear stress zones encountered during cutting into the dice shape, thus contributing to the high quality of the device being manufactured.
    Once one or more units are located within the cavity 303, the units may be mechanically unified with each other by sawing along the (vertical) edge 314. In this manner, a plurality of devices similar to 320 with ridges 312 that mimic conventional solder balls and have solderable surfaces 315 can be manufactured in a low cost process.
    Referring to FIG. 3D, the size of the ridge 312, given by the diameter 316 and height 317, is largely determined by the mechanical properties of the metal foil 307. In FIG. With appropriate microcrystalline and mechanical / thermal properties, copper foils of about 30 μm to 40 μm thickness may be stretched by about 15% to 22%. This means that a raised height of about 0.2 mm can be made for the required raised diameter of about 0.7 mm. With this height, 1.0 mm profile BGA and CSP devices can be fabricated that include the "ball" height at full thickness.
    Although the invention has been described with reference to the illustrated embodiments, this description should not be interpreted in a limiting sense. Various modifications and combinations of the embodiments shown, as well as other embodiments of the invention, are apparent to those skilled in the art upon reference to the description. By way of example, the material of the semiconductor chip may include silicon, silicon germanium, gallium arsenide or any other semiconductor material used in the manufacture. As another example, the shape of the shaped "ball" mimic bumps can be changed to an elongated structure by using a suitably flexible foil. Accordingly, the appended claims include any such modifications or embodiments.
    According to the invention, it is possible to eliminate the difficulty of positioning the preformed solder balls on the device package by creating ball-mimetic bumps simultaneously with the package, and between the casting composite and the metal foil used for electrical connection to the outside. By improving the adhesion, package reliability can be improved.
    权利要求:
    Claims (17)
    [1" claim-type="Currently amended] An integrated circuit chip having at least one input / output terminal,
    A body of encapsulated material formed around the chip forming a generally flat surface comprising at least one ridge having a size and shape suitable to mimic a solder ball,
    And said raised portion has a conductive solderable surface connected to said terminal.
    [2" claim-type="Currently amended] The semiconductor device according to claim 1, further comprising a layer of solder attached to said bump.
    [3" claim-type="Currently amended] The semiconductor device of claim 1, wherein the ridge has a size between about 0.5 mm and 0.75 mm in diameter and between about 0.1 mm and 0.25 mm in height.
    [4" claim-type="Currently amended] The semiconductor device of claim 1, wherein the conductive surface of the ridge comprises a metal foil having a thickness between about 10 μm and 75 μm.
    [5" claim-type="Currently amended] The semiconductor device of claim 4, wherein the raised conductive surface comprises a metal foil having a thickness between about 30 μm and 40 μm.
    [6" claim-type="Currently amended] The semiconductor device of claim 4, wherein the foil comprises a material selected from the group consisting of copper, copper alloys, iron-nickel alloys, aluminum, steel, and invar.
    [7" claim-type="Currently amended] 7. The solderable of claim 6 wherein the foil faces the outside of the ridge selected from the group consisting of copper, nickel, palladium, silver, gold, platinum, tin-lead, tin-silver, tin-indium and other solder alloys. A semiconductor device further comprising a surface.
    [8" claim-type="Currently amended] The semiconductor device according to claim 1, wherein the conductive surface of the ridge is connected to the chip terminal by the length of the bonding wire, and one end of the bonding wire is attached to the surface and the other end is attached to the terminal.
    [9" claim-type="Currently amended] The semiconductor device according to claim 1, wherein the ridge has a shape selected from the group consisting of hemispherical, truncated cone and truncated pyramid.
    [10" claim-type="Currently amended] The semiconductor device according to claim 1, wherein the bump is formed by a molding process for encapsulating the chip.
    [11" claim-type="Currently amended] Providing a plurality of integrated circuit chips each having a plurality of input / output terminals;
    Providing a conductive sheet-like substrate having a first surface and a second solderable surface;
    Attaching the chip on a first surface of the substrate and connecting terminals to the surface by wire bonding to form a plurality of substrate locations having welded wire bonds;
    Providing a mold having a lower half having a generally flat surface contour comprising a plurality of dimples of appropriate size and shape in an upper half and a solder ball, each having a cavity for holding a semiconductor device;
    Positioning the substrate in the lower half of the mold such that each wire bond position is aligned with one dimple, respectively;
    Encapsulating material presses the substrate against the surface contour of the mold lower half, and upon curing, the ridge closes the mold and presses the encapsulating material into the mold such that a wire bond is formed on the body of the encapsulating material at each position attached to the substrate. A semiconductor device manufacturing method comprising a.
    [12" claim-type="Currently amended] 12. The method of claim 11, further comprising opening the mold, electrically insulating the bumps from each other, and mechanically unifying the chips with each other to form an encapsulated semiconductor device.
    [13" claim-type="Currently amended] 13. The method of claim 12, further comprising depositing solder material on the second surface of the substrate covering the ridges.
    [14" claim-type="Currently amended] 13. The method of claim 12, wherein the electrically insulating process comprises a cutting process through the substrate material surrounding the ridges.
    [15" claim-type="Currently amended] A mold having an upper half and a lower half respectively having cavities for holding a semiconductor chip preassembled on a conductive substrate,
    And wherein one of the upper and lower halves has a generally flat surface profile comprising a plurality of dimples of a size and shape suitable to mimic a solder ball.
    [16" claim-type="Currently amended] 16. The apparatus of claim 15, wherein the dimple has a size between about 0.5 mm and 0.75 mm in diameter and between about 0.1 mm and 0.25 mm in depth.
    [17" claim-type="Currently amended] 16. The apparatus of claim 15, wherein the dimple has a shape selected from the group consisting of hemispherical, truncated cone, and truncated pyramid.
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    同族专利:
    公开号 | 公开日
    JP2000252389A|2000-09-14|
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    法律状态:
    1999-02-25|Priority to US12165899P
    1999-02-25|Priority to US60/121,658
    2000-02-24|Application filed by 윌리엄 비. 켐플러, 텍사스 인스트루먼츠 인코포레이티드
    2000-11-25|Publication of KR20000071375A
    优先权:
    申请号 | 申请日 | 专利标题
    US12165899P| true| 1999-02-25|1999-02-25|
    US60/121,658|1999-02-25|
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